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Chapter 4. Exploiting Instruction-Level Parallelism with Software Approaches. ???. ??????????. November 2004. EEF011 Computer Architecture. ?????
A Quantitative Approach, Fifth Edition Possibility of a hazard; Order in which results must be calculated; Upper bound on exploitable instruction level parallelism . Observation: if iterations from loops are independent, then can get more ILP by taking instructions from different iterations; Software pipelining: reorganizes
Exploits “Instruction Level Parallelism”. ? Beyond this, there are two main approaches: ? Hardware-based dynamic approaches. ? Used in server and desktop processors. ? Not used as extensively in PMP processors. ? Compiler-based static approaches. ? Not as successful outside of scientific applications. Introduction
Instruction-Level Parallelism 1. Concepts and Challenges. March 2014. 2. The potential overlap among instructions is called instruction-level parallelism (ILP). Two approaches exploiting ILP: Hardware discovers and exploit the parallelism dynamically. Software finds parallelism, statically at compile time. CPI for a pipelined
HW Support for More ILP X A = B op C Avoid branch prediction by turning branches into conditionally executed instructions: If (X) then A = B op C else NOP If false, then neither store result nor cause exception Expanded ISA of Alpha, MIPS, PowerPC, SPARC have conditional move; PA-RISC can annul any following
Software Approaches to Exploiting Instruction Level Parallelism. Lecture notes by: David A. Patterson. Boris Savkovic. 2. 1. Introduction. 2. Basic Pipeline Scheduling. 3. Instruction Level Parallelism and Dependencies. 4. Local Optimizations and Loops. 5. Global Scheduling Approaches. 6. HW Support for Aggressive
Exploiting ILP with. Software Approaches. 2. Outline. Basic Compiler Techniques for Exposing ILP; Static Branch Prediction; Static Multiple Issue: The VLIW Approach; Hardware Support for Exposing More Parallelism at Compiler Time; H.W verses S.W Solutions. 3. 4.1 Basic Compiler Techniques for Exposing ILP. 4.
4.1 Instruction Level Parallelism: Concepts and Challenges. 4.2 Overcoming Data Hazards with Dynamic Scheduling. 4.3 Reducing Branch Penalties with Dynamic Hardware Prediction. 4.4 Taking Advantage of More ILP with Multiple Issue. 4.5 Compiler Support for Exploiting ILP. 4.6 Hardware Support for Extracting more
Chapter 4: Exploiting Instruction-Level Parallelism with Software Approaches. 4-1. Chapter 4. Exploiting Instruction-Level Parallelism with Software Approaches. Rung-Bin Lin. Chapter 4: Exploiting Instruction-Level Parallelism with Software Approaches. 4-2. Basic Compiler Techniques for Exposing. Basic pipeline
Instruction-Level Parallelism (ILP). – Overlap the execution of instructions to improve performance. • 2 approaches to exploit ILP. 1. Rely on hardware to help discover and exploit the parallelism dynamically. – Pentium 4, AMD Opteron, IBM Power. 2. Rely on software technology to find parallelism, statically at compile-time.
     

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